Intel Haswell Signals Shifting Focus with Mobile Readiness and Power Efficiency

A couple of hours after noon on Tuesday June 4 in Asia, or an hour before midnight Monday in the Pacific Time zone, Intel is debuting its fourth-generation Core architecture, codenamed Haswell. The big splash is set to occur at Computex in Taipei, Taiwan, at Taipei World Trade Center Nangang Exhibition Hall. But many critical details about the Haswell — its power efficiency and mobile-friendliness in particular — have already been made public long before by Intel executives themselves. Here are a few revelations gleaned from conference previews in the last two years: Continue reading

Intel Xeon Phi Enters Parallel Quest for HPC Dominance

Ever seen three thoroughbreds heading for the same finishing line, but running on different tracks? Watch AMD, Intel, and NVIDIA going after the high-performance computing (HPC) market. This week, Intel entered an official name into the race, Intel Xeon Phi. The first product to feature Intel’s many integrated core (MIC) architecture, Phi is expected to ship with more than 50 cores. Continue reading

AMD Fusion Developer Summit: GPU is Not Just for Ninja Programmers

Skilled programmers who can sneak into the GPU and execute their parallel jobs belong to an elite group. They are “Ninja programmers,” as AMD corporate fellow Phil Rogers call them.

Rogers, who delivered the keynote at this week’s AMD Fusion Developer Summit, believes GPU computing should be available to a broader audience, to the common programmers who make a living churning out codes in C, C++, JAVA, and Python. In fact, Rogers may even object to the term GPU computing. If it were up to AMD and Rogers, GPU and CPU computing could be one and the same, fused together into a Heterogeneous System Architecture (HSA). Continue reading

Intel Xeon E5-2600, a Better Traffic Cop for the Cloud

On March 6, as commuters in the West Coast begrudgingly joined the morning’s rush hour traffic, Intel unveiled what could be the solution to heavy traffic in the Cloud.

At 9 AM Pacific, Diane Bryant, the newly appointed vice president and general manager of Intel’s Datacenter and Connected Systems Group, took the stage at the Contemporary Jewish Museum (San Francisco, California) to launch the Intel Xeon E5-2600 family, described by Intel as “the heart of a flexible, efficient data center.” Continue reading

Intel Knights Preparing for Parallel Battle

CPU maker Intel‘s new architecture, dubbed Knights Corner, represents the move from multicore (two, four, six, eight …) to many integrated cores (MIC, more than 50 Intel processing cores on a single chip).

Intel describes MIC as a coprocessor, a power-booster to the central processor. The new product is expected to be a serious contender in the high performance computing (HPC) market, where graphics coprocessors (GPUs) have been grabbing market shares because of their parallel computing capability. What distinguishes Intel’s MIC from graphics coprocessors may be its programming environment. Continue reading