Nanotubes Lead Way to Faster Chips
IBM scientists at the T.J. Watson Research Center have come up with a way to use carbon nanotubes to build faster, smaller microprocessors with more transistors.
The research, which appeared in a recent edition of Nature Nanotechnology, involves creating an array of carbon nanotubes on the surface of a silicon wafer to build chips with more than 10,000 transistors. IBM has done so at a scale where silicon simply doesn’t work, and by packing so many transistors on to such a tiny area could boost CPU performance significantly.
The development could help maintain the pace of chip performance the technology industry has come to rely on. IBM hopes the technology can increase the speed of chips, while simultaneously increasing the number of transistors available, breaking the clock speed logjam, and perpetuating Moore’s Law in the process, even as silicon chips reach their physical limits.
The innovation in the IBM research is the process the researchers came up with to create regular arrays of the nanotubes. By placing them in a soapy mixture, the team created patterned arrays (via “chemical self-assembly”). This ion-exchange chemistry method allows “precise and controlled placement of aligned carbon nanotubes on a substrate at a high density,” the company said.
“Carbon nanotubes, borne out of chemistry, have largely been laboratory curiosities as far as microelectronic applications are concerned. We are attempting the first steps towards a technology by fabricating carbon nanotube transistors within a conventional wafer fabrication infrastructure,” said Supratik Guha, director of Physical Sciences at IBM Research. “The motivation to work on carbon nanotube transistors is that at extremely small nanoscale dimensions, they outperform transistors made from any other material. However, there are challenges to address such as ultra high purity of the carbon nanotubes and deliberate placement at the nanoscale. We have been making significant strides in both.”
Source: New York Times