Zuken has announced CADSTAR 15. The solution’s P.R.Editor now supports impedance balanced routing that simplifies the implementation of high-speed interfaces. Engineers can route to JEDEC standards and meet DDR3 performance specifications. This reduces design iterations by helping designers optimize circuits for the highest clock speeds, the company says.
Improved eye patterns in CADSTAR 15 include automatic measurement of eye height/width and setup/hold. New features in Power Integrity Advance include adjustable gridding for common-mode voltage maps, decoupling capacitor improvements, and a common user interface for result display in all signal integrity and power integrity analysis tools.
A new panel for item properties gives modeless (docked, floating or auto-hide) operation in Design Editor and Library Editor. This reduces the number of steps to modify the properties of all item types in the design, and allows multi-item selection and changes.
For more information, visit Zuken.
Sources: Press materials received from the company and additional information gleaned from the company’s website.