Home / Design / Zuken Promotes Smarter Teamwork with CR-8000 System Planner and Design Gateway 2014

Zuken Promotes Smarter Teamwork with CR-8000 System Planner and Design Gateway 2014

Zuken has added new team design capabilities with new versions of its System Planner and Design Gateway software, part of the CR-8000 single and multi-board design solution.

System Planner and Design Gateway are at the core of Zuken’s CR-8000 2D/3D single and multi-PCB and IC packaging design solution, and contain enhancements that allow teams of engineers to work concurrently on the same design, new checks to ensure integrity in hierarchical and system level designs, and enhanced generation of intelligent PDF data to aid design communication.

Each System Planner module can be opened by concurrent users. This allows multi-disciplinary development teams to work on the same design. Detailed circuits generated in System Planner are bi-directionally synchronized with Design Gateway. When a Design Gateway schematic is updated, for example, when reference designators are changed, the updates are reflected in System Planner’s visionaries.

Information on connections between hierarchy levels is readily available in the new Hierarchy Connection View browser. Design Gateway has several new checks to detect connectivity errors across hierarchical and system level designs. Users can easily confirm connection consistency between block pins and their associated nets, hierarchical pins and their associated nets, signals routed through multiple boards, and net properties between multiple boards.

Design Gateway supports the generation of intelligent PDF data including bookmarks, item properties, and navigation of hierarchical designs within the PDF document. This provides detailed design information to system architects, PCB designers, manufacturers and others who may not have access to Design Gateway.

Constraint information is directly associated with functional blocks within Design Gateway, enabling copying and editing of constraints on a block basis. Constraints can be managed at the block level and the constraints associated with reuse circuits are reusable.

For more information, visit Zuken.

Sources: Press materials received from the company and additional information gleaned from the company’s website.

About DE Editors

DE's editors contribute news and new product announcements to Desktop Engineering. Press releases can be sent to them via DE-Editors@deskeng.com.