Silicon Frontline Technology Inc., an electronic design automation (EDA) company in the post-layout verification market, announced that new versions of its F3D (Fast 3D) for 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures like power devices, are shipping. According to the company, F3D improves its performance by up to 10x when compared to the previous version. F3D and R3D also accommodate larger designs than the previous versions. The latest version of Silicon Frontline’s 3D Field Solver technology accomplishes full-chip extraction with Field Solver accuracy and improves its performance and capacity. A tiling feature allows design size for F3D and R3D to be unlimited, according to the company. Designs can be automatically partitioned into blocks of up to 4-million transistors and each block can be run using one CPU or multiple CPUs can run a number of design blocks in parallel. In the previous version the block size was limited to a maximum of 1 million transistors. F3D is suited for sensitive analog and AMS circuits where coupling is a challenge. R3D target applications include discrete or embedded power devices, as well as designs requiring analysis of large metal interconnects. For more information, visit Silicon Frontline Technology. Sources: Press materials received from the company and additional information gleaned from the company's website.
|
